The present invention relates to a semiconductor device including a layer which contains Si and Ge and a method for fabricating the same, and more particularly relates to a semiconductor device which includes a SiGe layer or a SiGeC layer and is isolated from adjacent semiconductor devices by trench isolation and a method for fabricating the same.
In recent years, research and development has been actively carried out on heterojunction field effect transistors, heterojunction bipolar transistors, and like devices using an Si1−xGex(0<x<1) layer (which will be herein referred to as an “SiGe layer”) of a mixed crystal of silicon (Si) and germanium (Ge).
As for heterojunction devices using a SiGe layer, with increased carrier mobility in the SiGe layer, high speed operation can be achieved. In addition, process steps for fabricating devices using a SiGe layer (which will be herein referred to as “SiGe devices”) can be used interchangeably with those for fabricating devices using an Si layer (which will be herein referred to as “Si devices”). Thus, fabrication techniques and production lines for use in fabricating Si devices can be used in most of the process steps for fabricating SiGe devices. Therefore, it is also possible to integrate SiGe devices on an Si substrate. As can be seen from the above, SiGe devices exhibit excellent properties in terms of performance and cost.
When a large number of SiGe devices are integrated on an Si substrate, isolation techniques for electrically insulating one device from another are critical as in the case of integrating known Si devices.
As known isolation techniques, local oxidation of silicon (LOCOS) and trench isolation techniques have been used. When a LOCOS technique is used, however, there may be cases in which so-called birds' beaks are formed so that an oxide film for isolating devices from each other enters into a transistor forming region. In such a case, the area of the transistor forming region is reduced, and therefore it is difficult to avoid this situation and to achieve reduction in the size of integrated circuits at the same time. Thus, trench isolation techniques which can isolate one device from another without causing reduction in the area of the transistor forming region are the mainstream isolation techniques for integrated circuits in accordance with the recent rules for size reduction.
Hereinafter, isolation techniques for isolating devices including a SiGe layer will be described. In Japanese Unexamined Patent Publication No. 10-321733 (U.S. Pat. No. 6,111,267), using a LOCOS technique, devices including a SiGe layer are isolated from each other. However, for the reason described above, trench isolation techniques are now expected to be the mainstream isolation techniques for isolating SiGe devices, as in the case of isolating Si devices. Trench isolation techniques for forming a trench isolation can be roughly divided into two types. One is the type in which a trench is formed before a SiGe layer is formed. The other is the type in which a trench is formed after a SiGe layer has been formed.
Hereinafter, a method for fabricating a semiconductor device in which a trench isolation is formed before forming a SiGe layer on a substrate will be first described. In this method, the process step of forming a trench isolation is performed before the process step of forming a SiGe layer, and thus process steps of a known method for fabricating an Si device can be used. This method, however, may cause some inconveniences. For example, assume that a SiGe layer is epitaxially grown on a substrate in which a trench isolation has been formed. If the SiGe layer has been non-selectively grown, a polycrystalline SiGe layer may be formed on an oxide film and/or a polycrystalline silicon film, resulting in the generation of leakage current. If the SiGe layer is selectively grown, facets may be created in the peripheral portion (boundary portion) of part of the substrate in which the SiGe layer is selectively grown, thus resulting in fluctuation of the threshold voltage of a device.
Next, a method for fabricating a semiconductor device in which a trench isolation is formed after a SiGe layer has been formed on a substrate will be hereinafter described with reference to FIGS. 10A through 10E. FIGS. 10A through 10E are cross-sectional views illustrating respective process steps for forming a trench isolation in a substrate on which a SiGe layer has been formed in a known fabrication method. Note that in the process steps shown in FIGS. 10A through 10E, a trench isolation is formed by the same process steps as those for forming a trench isolation in a known Si device.
First, in the process step shown in FIG. 10A, an Si buffer layer 102 having a thickness of 10 nm, a SiGe layer 103 having a 25% Ge content and a thickness of 15 nm and, an Si cap layer 104 having a thickness of 15 nm are epitaxially grown by UHV-CVD on an Si substrate 101 containing an n-type impurity at a concentration of 1×1018 cm−3. In the UHV-CVD, Si2H6 (disilane) and GeH4 (germane) are used as source gasses of Si and Ge, respectively. The growth temperature is 550° C. and no intentional doping is performed. Note that the semiconductor substrate is divided into an active layer forming region Rac and an isolation region Rre for convenience of description.
Next, in the process step shown in FIG. 10B, a silicon thermal oxide film 105 is formed by thermally oxidizing an upper portion of the Si cap layer 104. With this thermal oxidation, the upper portion of the Si cap layer 104 is oxidized to be a thermal oxide film, and therefore the thickness of the Si cap layer 104 becomes about 8 nm. Note that the thermal oxidation temperature is 750° C. Thereafter, a silicon nitride film 106 having a thickness of 210 nm is formed on the silicon thermal oxidation film 105. Note that the deposition temperature for the silicon nitride film 106 is 740° C. In this case, when each of the silicon thermal oxide film 105 and the silicon nitride film 106 is formed at a lower temperature, it is possible to prevent defects from generating due to relaxation of the strained SiGe layer 103 formed on an Si crystalline layer.
Then, parts of the silicon nitride film 106 and the silicon thermal oxide film 105 located in the isolation region Rre are removed by anisotropic dry etching. Subsequently, the Si cap layer 104, the SiGe layer 103, the Si buffer layer 102 and an upper portion of the Si substrate 101 are patterned using as a mask remaining parts of the silicon nitride film 106 and the silicon thermal oxide film 105 located in the active layer forming region Rac. In this manner, a trench 107a is formed so as to have a depth of about 0.4 ì m to 0.8 ì m and reach to the Si substrate 101. In this case, the side faces of the SiGe layer 103 are exposed at the side surfaces of the trench 107a by forming the trench 107a. 
Next, in the process step shown in FIG. 10C, the surface of the trench 107a is thermally oxidized at 750° C., thereby forming a trench surface coating film 108 so as to coat the surface of the trench 107a. 
Next, in the process step shown in FIG. 10D, an oxide film is formed on the substrate, and then part of the oxide film located in the active layer forming region Rac is removed by etch-back or CMP (chemical mechanical polish). In this manner, a trench oxide film 109 is formed so as to fill the trench 107a. Thus, active regions are isolated from each other by a trench isolation 107 including the trench oxide film 109 and the trench surface coating film 108.
Next, in the process step shown in FIG. 10E, remaining parts of the silicon nitride film 106 and the silicon thermal oxide film 105 located in the active layer forming region Rac in the substrate are removed by etching, so that part of the Si cap layer 104 located in the active layer forming region Rac is exposed.
In connection with the fabrication of a semiconductor device including a layer containing Si and Ge, a process step for forming an oxide film by thermally oxidizing a surface portion of a trench in the above-described manner is disclosed in Japanese Unexamined Patent Publication No. 10-74943 (U.S. Pat. No. 6,191,432). Furthermore, in the publication, disclosed is a semiconductor device fabrication method in which an Si layer having a thickness of about 5 nm to 50 nm is formed in a surface portion of a trench and then the Si layer is oxidized. This method is also disclosed in Japanese Examined Patent Publication No. 6-80725 (U.S. Pat. No. 5,266,813 and U.S. Pat. No. 5,308,785).
Now, a semiconductor device including a trench isolation formed in the process steps shown in FIGS. 10A through 10E, i.e., a p-type MOSFET in which a SiGe layer serves as a hole channel (SiGe p-MOSFET) will be described with reference to FIGS. 11A and 11B. FIGS. 11A and 11B are cross-sectional and plane views illustrating the structure of the p-type MOSFET including a trench isolation formed in a known manner. FIG. 1A is a cross-sectional view taken along the line XI—XI shown in FIG. 11B.
An Si buffer layer 102, a SiGe layer 103, and an Si cap layer 104 are formed on part of an Si substrate 101 located in an active layer forming region Rac. On the Si cap layer 104, a gate electrode 111 is formed with a gate insulating film 110 interposed between the Si cap layer 104 and the gate electrode 111. Source/drain regions 112 heavily doped with p-type ions are provided in parts of the Si cap layer 104, the SiGe layer 103, the Si buffer layer 102, and the Si substrate 101 located on both sides of the gate electrode 111 so as to be spaced apart from each other. Then, parts of the Si cap layer 104, the SiGe layer 103, the Si buffer layer 102, and the Si substrate 101 located under the gate electrode 111, i.e., parts of the layers located between the source/drain regions 112, serve as a channel region.
In an isolation region Rre of the Si substrate, a trench isolation 107 including a trench oxide film 109 and a trench surface coating film 108 coating the trench oxide film 109 is formed. With the trench isolation 107, parts of the active layer forming region Rac which are to be active regions are isolated from each other.
On the Si cap layer 104 and the trench isolation 107, an interlevel insulating film 114 is formed so as to cover the gate electrode 111. Then, an interconnect 115 of, e.g., Al is formed so as to reach the source/drain region 112 through the interlevel insulating film 114 and an SiO2 film. A known p-MOSFET including a trench isolation has the above-described structure.
As for the SiGe p-MOSFET of FIGS. 11A and 11B, however, when a trench isolation is formed in the known process steps described in FIGS. 10A through 10E, the following inconveniences occur.
In the process step shown in FIG. 10C, thermal oxidation is performed with the side faces of the SiGe layer 103 being exposed at the side surfaces of the trench 107a. Thus, the trench surface coating film 108 is formed. As the thermal oxidation process proceeds, Si is oxidized in the side faces of the SiGe layer 103 exposed at the side surfaces of the trench 107a and also in part of the SiGe layer 103 located close to the exposed side faces. Thus, the part of the SiGe layer 103 in which Si has been oxidized becomes parts of the trench surface coating film 108 formed of SiO2, and Ge is expelled from the trench surface coating film 108. As a result, when the thermal oxidation process is finished, Ge segregates at the interface between the trench surface coating film 108 and part of the SiGe layer 103 which has not been oxidized, thereby forming a layer containing Ge at a high concentration. Also, there have been reported cases in which depending on conditions for thermal oxidation, regions containing a high concentration of Ge are formed and distributed like islands in the trench surface coating film 108. Moreover, Ge segregates in edge portions of the channel region located under the gate electrode and at the interface between the active layer forming region Rac and the isolation region Rre, resulting in a Ge segregation layer 116, as shown in FIG. 11B.
Naturally, more interface states are generated at the interface between an SiO2 layer and a SiGe layer than at the interface between an SiO2 layer and an Si layer. If many interface states are generated, threshold voltage in a device may fluctuate. Interface states may also form a channel for leakage current flowing between the source and the drain in a transistor or between different transistors.
The existence of part of the substrate which contain Ge at a high concentration between the trench surface coating film 108 and the SiGe layer 103 may also cause fluctuation in threshold voltage.
FIG. 12 is a graph showing drain current-gate voltage characteristics in the SiGe p-MOSFET shown in FIGS. 11A and 11B. The data shown in the graph of FIG. 12 was obtained by measurements under the conditions in which both of the gate length and the gate width were 50 ì m and a source-drain voltage of −300 mV was applied. The graph shows that transistor properties have been degenerated due to the above-described inconveniences, such as an increase in leakage current and fluctuation in threshold voltage.
Ge segregation in performing thermal oxidation occurs not only in the process step of forming a trench but also in the process step of forming a gate oxide film on the SiGe layer. Then, in such a case, a gate oxide film has to be formed by oxidizing an Si cap layer with the SiGe layer covered by the Si cap layer.
Moreover, when an Si1−x−yGexCy (0<x<1, 0≦y<1) layer (which will be herein referred to as “a SiGeC layer”) is thermally oxidized, Ge segregation also occurs.